Wireless transmitters and receivers may include one or more voltage controlled oscillators (VCO) of which very little variation of the oscillating frequencies is tolerated. The oscillating frequency of a voltage-controlled oscillator may be conventionally set and dynamically adjusted to a reference frequency value by means of a phase-locked loop (PLL). The phase-locked loop operates under control of an error signal representative of the phase and frequency differential between the reference signal oscillating at the reference frequency and a signal representative of the divided oscillating signal of the voltage controlled oscillator.
It has been long desirable in the art to enable a PLL to lock to the reference frequency in the least possible amount of time. A possible way of reducing the locking time of a frequency synthesizer is to charge the loop filter with a higher charge pump current than in its normal mode of operation. This current may be controlled by external circuitry. The locking time depends on the charge pump and on how much current the charge pump can deliver to the capacitors of the loop filter of the PLL and thus increasing this current to a certain extent accelerates the initial charging of the capacitors of the loop filter.
Another possible method for adjusting the voltage controlled oscillator frequency is described in European Patent Specification No 0402113B1. EP 0402113B1 gives a circuit for setting the free-running frequency of a voltage-controlled oscillator in a phase locked loop (PLL). The circuit comprises a digital to analog converter (DAC) in the PLL with the output of the DAC being connected to the input of the VCO. The output of the DAC represents substantially the center of a pre-selected PLL lock range. A frequency locked loop (FLL) initially sets the free-running frequency of the VCO to a pre-selected value. The FLL is also used to dynamically adjust the free-running frequency to maintain it within the pre-selected lock range of the PLL in the event of drift due to relatively large changes in supply voltage and/or temperature. The FLL may comprise a digital processing unit and a DAC. Initially the PLL is disabled and while the PLL is disabled, the FLL sets up the free-running frequency. The frequency of the VCO is compared with reference clock pulses from a source and based on the comparison the DAC input controlling the free-running frequency is gradually adjusted by increments or decrements of 1.